Cache memory systems have been utilized in modern computer systems to enable the system to operate at a much higher rate of execution with the large capacities that main memories can support. The cache memory stores a limited number of instruction or data words that are readily accessed by a central processing unit. During acquisition of data or instructions from memory, the cache is first examined to determine if the information is available therein. If the information is stored therein, it will be read from cache memory; otherwise, it will be read from main memory. When the information must be read from main memory, this new information is then stored in the cache memory and replaces already existing information therein. To determine the information in the cache that is to be replaced, a determination is made as to which data or instructions stored in the cache memory have been least recently accessed or "least recently used". By so doing, data or instructions that are most commonly used will statistically be available in the cache memory, thereby increasing execution speed of a given system.
In utilizing a least recently used system, it is necessary to determine priority between the various registers in given cache memory. There are various methods that have been utilized in the past for accomplishing this, such as that disclosed in U.S. Pat. No. 4,458,310, issued to Shih-Jeh Chang and assigned to AT&T Bell Laboratories. Essentially, it is necessary to utilize additional memory for the storage of information corresponding to the priority of the various data registers. This is facilitated by pointers or the like. However, implementation of least recently used systems has proven to be difficult and requires a large amount of circuitry and time consuming processing techniques.
In addition to determining the priority of a given memory location in a cache, the addressing of cache memory also presents a problem when utilized in a system of multiple processors with multiple caches. In a system of this form, the main memory and caches operate in a physical addressing medium, whereas the multiple processors operate in a virtual addressing medium. Therefore, a processor must make a translation from virtual to physical addressing in order to access its associated cache. This presents a disadvantage in that a predetermined amount of processing time is required to perform this translation, which can decrease execution speed. Therefore, it would be desirous to have a cache memory which recognizes both the virtual and physical addresses such that either type of address can be directly utilized with a cache memory, thereby eliminating the virtual to physical translation time.
In fabricating cache memories, it is necessary that all accessible memory locations be operable such that errors are not introduced when the memory is incorporated into a system. Although a defective location may be tolerated in an N-way associative set, it is first necessary to deactivate this defective location such that an attempt is not made to store data therein or read data therefrom. This has been facilitated in the prior art by determining which data register is defective upon power up of a system and storing this information in a memory. Circuitry is then utilized to inhibit access to the faulty portion of the cache memory. A system of this type is described in Architecture of a VLSI Instruction Cache for a RISC, Patterson et. al., 10th International Symposium on COMPUTER ARCHITECTURE, Jun. 13-16, 1983. However, this requires complicated circuitry and scanning of the system prior to activation of the system.
In view of the above disadvantages, there exists a need for an architecture which allows a system to directly communicate with a cache through both physical or virtual addresses and also to determine which data register in a given cache is the least recently accessed data in a reliable and efficient manner.